Scientech SDR objective is to provide a hands-on learning experience using SDR for engineering students, researcher and industry practitioners who are interested in mastering in software-defined radio (SDR), radio frequency (RF), and wireless communications

Scientech SDR comes with built-in experiments so students can learn faster and explore more.


  • Portable design.
  • Designed around wireless industry, research & academic need.
  • Block level approach.
  • RF-up converter from 400MHz to 4GHz.
  • RF-down converter from 40MHz to 3GHz.
  • Fully programmable.
  • Control & acquisition for real-time signal time domain analysis on software.
  • Built-in Low-noise frequency synthesizer.
  • Built-in JTAG for FPGA configuration.
  • Interface: Ethernet


  • It allows engineers to prototype and test wireless communication applications.
  • It comes along with standard built-in modules which will help engineers to kick start their wireless communication journey.
  • It allows rapid prototyping of high performance wireless communication system.

Product Video

System Architecture

Things you can do

  • Install and understand the complete Software Defined Radio setup.
  • Perform and understand unmodulated carrier in frequency domain using Spectrum Analyzer.
  • Establish, analyze and verify end to end wireless communication link between Transmitter and Receiver using test data and BPSK baseband modulation & demodulation.
  • Establish wireless MSK & GMSK modulation and demodulation complete link
  • Understanding BER measurement.
  • Understanding the effect of AWGN noise over end to end wireless communication link.
  • In addition to pre loaded built-in modules users can also implement their wireless communication applications.

Technical Specifications

SDR Transmitter & Receiver

  • Maximum Symbol Rate: up to 40 Mbps.
  • Device Xilinx Artix7 FPGA (XC7A100T-1) for massive parallel computing.
  • Dual 500 MSPS 16-bit D/A converters for I Channel and Q Channel.
  • 14 bit ADC with 100 MHz internal sampling clock.
  • 6-pole Butterworth clock rejection filters.
  • Wideband modulation bandwidth > 200MHz.
  • DAC clock rejection @ 40 MHz > 84 dBc.
  • Output voltage: 1Vpp with 0.85V DC bias.
  • Built-in JTAG USB connector for FPGA configuration.
  • Standard built-in modulations like BPSK, QPSK, & OQPSK.
  • Digital Filters: Raised Root Cosine with variable roll-off with interpolation and decimation facility.
  • Built-in channel impairments generation: AWGN and frequency offset (Doppler)
  • Built-in real time Software for Transmitter signal analysis.
  • Built-in Data Generator as test pattern.
  • 400MHz to 4GHz Quadrature Modulator.
  • 400MHz to 3GHz Quadrature De-modulator.
  • Fixed 10 MHz Local Oscillator (±2.5PPM).
  • Low-noise frequency synthesizer can be tuned over entire range by steps of 100, 31.25 or 25 KHz.
  • Built in RF AGC.
  • Ethernet port for data, control and monitor.
  • SMA connector.
For more information please feel free to contact us.

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