Universal Embedded Development Platform



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Scientech 116 Universal Embedded Development Platform has been designed to provide a quick and easy way of learning and implementing VLSI front end & Embedded design. Using Scientech 116 you will be able to design a high end design based on FPGA, Controller and DSP applications.

Scope of Learning

  • Digital Boolean logics, Multiplexers, De-multiplexers, Encoders, Decoder, Priority encoder, Code Converter, Parity Generator, Latches and Flip-Flop, Shift Registers, BCD Counter, Address Decoders, ALU.
  • 32 bit Controller programming, ARM mode/ Thumb mode, ADC/DAC programming, RTOS – signal, semaphore, mailbox and scheduling algorithms, study of PWM, External Interrupts, UART, I2C, SPI protocol and USB protocol.
  • 32 Bit DSP Controller F2812 learning by PWM generation using Event manager ADC, UART, I/O port Programing etc.


  • Embedded platform for FPGA and Controller/DSP applications
  • Daughter cards for FPGA and Controller for extended technology
  • Mother board with flexible architecture
  • Xilinx Spartan 3 FPGA Daughter Card
  • ARM7TDMI-S 32 Bit LPC2148 microcontroller
  • DSP TMS320F2812 fixed point 32 bit DSP Controller
  • On board logic input/output/Push Buttons
  • On board USB for external communication
  • Provision for connecting VB-series application boards (VB01 to VB19)
  • Provision for connecting MC-series application boards (MC01 to MC17)
  • 8-bit Communication provision between FPGA and Controller/DSP
  • Interfacing 16X2 LCD with DSP/Controller
  • Interfacing Hex keypad with DSP/Controller
  • Interfacing Seven Segment Display with DSP/Controller
  • Interfacing Switches/Buzzer with DSP/Controller
  • Xilinx CPLD Daughter Card (optional)
  • Xilinx Cool Runner CPLD Daughter Card (optional)
  • Xilinx Spartan 3E FPGA Daughter Card (optional)
  • Altera Cyclone-II FPGA Daughter Card (optional)
  • 2 Year Warranty


  • Simulink Module for DSP Controller and ARM7
  • MATLAB library for interfacing serial port of DSP Controller and ARM7

Product Video

Technical Specifications

Technical Specification Mother Board

On board
+5V, 3.3V Supply
DIP switches
Output LEDs
Push button
USB to serial converter Interfacing
for VB-series board interfacing
for MC-series board interfacing
Power Supply
100 - 260V AC, 50/60 Hz
Dimension (mm)
W 326 x D 252 113 x H 52
2.5 Kg (approximately)
Operating Condition
0-40 C, 85% RH

ARM7 Daughter Card

Crystal frequency
12 MHz
On-Chip Static RAM
On-Chip Flash Memory
Programmer mode selection
Run/ISP Switch
Internal USB
Analog to Digital Converter
10-bit A/D converters provide a total of
6/14 analog inputs
Digital to Analog Converter
10-bit D/A Converter
Two 32-bit timer/External event Counter
Pulse Width Modulation
Six outputs
Real Time Clock
Low Power RTC
Multiple serial interfaces including two UARTs
Two Fast I2C-bus
SPI and SSP with buffering and variable
data length capabilities
External Interrupts
Nine edge or level sensitive
external interrupt pins

System Requirement

Operating Systems
Windows XP / 7 / 8 - 32 bit
Minimum 2GB

DSP Daughter Dard

Device Family
TMS 320 F 2812
Device density
32 bit DSP Micorcontroller
128 KB flash memory
Programming methods
SCIA Serial port ( on board) USB JTAG (optional)
Crystal frequency
30 MHz
On-Chip Memory
Flash Devices: Up to 128K x 16
ROM Devices
Up to 128K x 16 ROM
External Interrupts
Motor Control Peripherals
Two Event Managers (EVA, EVB)
Serial Port Peripherals
Serial Peripheral Interface (SPI)Two Serial Communications Interfaces(SCIs), Standard UART Enhanced Controller Area Network (eCAN) Multichannel Buffered Serial Port (McBSP)
Analog to Digital converter
12-Bit ADC, 16 Channels
I/O pins
Up to 56 General-Purpose I/O (GPIO) Pins
Development Tools Include
ANSIC/C++ Compiler/Assembler/Linker Code Composer Studio IDE 5.4 version DSP/BIOS(Real Time Kernel) Evaluation version

FPGA Daughter Card

Xilinx family
Spartan 3, XC3S400PQ208
Device density
400k gates
On board
8 MHz crystal
Master reset key
For hardware reset
On board
EPROM for FPGA boot
Configuration Method
JTAG / boundary scan interface

Optional Daughter Card

CPLD Daughter Card

Xilinx family
CPLD, XC95108TQ100
Device density
2400 gates, 108 macro cells
On board
8 MHz crystal
Configuration method
JTAG interface (boundary scan)

Spartan3E FPGA Daughter Card

Xilinx Family
Spartan 3E, XC3S500EPQ208
Device density
500k gates
On board
8 MHz crystal
Master reset key
For hardware reset
On board
EPROM for FPGA boot
Configuration method
JTAG /boundary scan inter face,PROM interface

Cool Runner CPLD Daughter Card

Xilinx family
Cool Runner XCR3128
Device density
28 macrocells
On board
8 MHz crystal
Configuration Method
JTAG /Boundary scan interface

Altera Cyclone II FPGA Daughter Card

Cyclone II
Number of logic elements/cells
Number of free dedicated input
Number of clocks
USB Blaster configuration cable
Quartus II web edition

AVR ATMEGA128 Daughter Card

Device family
64-pad TQFP
Device density
8-bit AVR microcontroller 128 KB flash memory
Programming methods
USB Programmer

PIC32 Daughter Card

Device family
TQFP 100-Pin
Device density
32-bit PIC microcontroller 512 KB flash memory
Programming methods
Pickit3 Programmer

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